For large-scale display panels and/or high-definition television (HDTV) monitors, it may be desirable to increase the data bit width and/or the number of channels used for data transmission in order to potentially increase the number of colors and/or the image quality of the display. Accordingly, it may be desirable to transmit data signals to the display at high speed and/or with low power consumption, and/or to reduce electromagnetic interference (EMI) generated in or near the display.
A data signal is typically transmitted via a transmission line as a digital signal. However, if the range of voltage swing of the data signal is reduced from a high voltage swing to low voltage swing in order to facilitate high-speed data transmission, the signal may be susceptible to noise, which may interfere with the signal. Differential signal transmission, in which data is transmitted via two lines, was introduced partly to address this problem.
FIG. 1A is a schematic circuit diagram of a transmitting and receiving apparatus 10 that transmits differential signals via two lines. Referring to FIG. 1A, the apparatus 10 includes a transmitting unit 20, a transportation unit 30, and a receiving unit 40. The transmitting unit 20 transforms a data signal D0, which is to be transmitted, into differential signals via a differential signal generator 21, and transmits the differential signals to output pads 22 and 23.
Then, the differential signals are supplied to pads 41 and 42 of the receiving unit 40 via lines 31 and 32, respectively. The supplied differential signals are matched by a termination resistor R between the lines 31 and 32, and voltages developed across the termination resistor R by the differential signals are amplified by an amplifier 43.
The polarity of the voltage developed across the termination resistor R, which is determined by the direction of current flowing through the termination resistor R, may represent one of two states (i.e. a logic low state or a logic high state). Therefore, two-state data (i.e., log2 2-bit, or 1-bit data) can be transmitted via two lines 31 and 32. In this case, the transmission efficiency is 0.5 bits per line. However, the transmission efficiency of a differential signaling system may be increased by using three lines instead of two lines. Such a system may be referred to as a ternary line differential signaling system.
FIG. 1B is a schematic circuit diagram of a data transmitting and receiving system 100 that transmits data signals via ternary lines 121, 122, 123. Referring to FIG. 1B, the system 100 includes a transmitting unit 110, a transportation unit 120, and a receiving unit 130. The transmitting unit 110 includes an encoder block 111 that is configured to transmit a clock signal CLK and data signals D1, and D2 via ternary lines 121, 122, and 123. The encoder block 111 encodes the clock signal CLK so that the clock signal CLK can be transmitted together with the data signals D1 and D2 via the same line. The encoder block 111 drives current flowing through the transmitting unit 110 to generate a voltage difference having a magnitude and polarity that depends on the direction of current flowing through termination resistors R1, R2, and R3, respectively, of the receiving unit 130.
The receiving unit 130 receives signals transmitted via the lines 121, 122, and 123 of the transportation unit 120. The magnitudes and polarities of the voltages developed across the termination resistors R1, R2, and R3 are determined by the directions of the currents respectively flowing through the termination resistors R1, R2, and R3, based on the received signals.
If voltages between two resistors selected from the termination resistors R1, R2, and R3 are used for differential signal amplification, data signals having six different states may be generated. A decoder 134 of the receiving unit 130 receives the differentially amplified signals and restores the clock signal CLK and the data signals D1 and D2. Therefore, it is possible to transmit six-state data, i.e., 2.56 (=log2 6)-bit data, via ternary lines 121, 122, and 123. In this case, the transmission efficiency is approximately 0.86 bits per line.
Accordingly, as described above, when differential signals are transmitted via ternary lines, it may be possible to increase the transmission efficiency of a differential signaling system. In addition, it may be possible to reduce manufacturing costs, since the number of lines per bit required is reduced, and/or to reduce noise such as EMI. However, if the transmission unit 110 transmits the clock signal CLK together with the data signals D1 and D2 via the same line, data may not be precisely recovered if the skew between the clock signal CLK and one or more of the data signals D1 or D2, which are restored by the receiving unit 130, is large.
FIG. 2A is a waveform diagram of voltages V(P), V(S), and V(T) of signals supplied to the receiving unit 130 of FIG. 1B. That is V(P) is a waveform of a voltage at node P of FIG. 2A, V(S) is a waveform of a voltage at node S of FIG. 2A, and V(T) is a waveform of a voltage at node T of FIG. 2A. FIG. 2B illustrates some possible values of the difference between two voltages selected from voltages V(P), V(S), and V(T) of the termination resistors R1, R2, and R3 of the receiving unit 130.
Referring to FIGS. 2A and 2B, an instant of time (t1 or t2) when the magnitude of two voltages V(P) and V(S), or V(P) and V(T), which are selected from the voltages V(P), V(S), and V(T) of the supplied signals, is changed, thus causing differential amplifiers 131, 132, and 133 of the receiving unit 130 to be driven at different times. Thus, when outputs of the differential amplifiers 131, 132, and 133 are restored by the decoder 134, there may be a skew between the clock signal CLK and the data signal D1 or D2. The skew between the clock signal CLK and the data signal D1 or D2 may interfere with the transmission of data.
The difference between two selected from voltages V(P), V(S), and V(T) of the supplied signals may have six possible state values, e.g., ±100 mV, ±200 mV, and ±300 mV. Thus, the six state values have 3 different magnitudes.
Accordingly, it may be desirable to reduce skew between the clock and data signals of a high speed ternary differential signaling system.